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The output-pin slew rate is determined by V DD voltage
and the load on the output. It is not user adjustable, but
if a slower rise or fall time at the MOSFET gate is
needed, a series resistor can be added.
?
?
?
Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the series inductance to improve high-
speed switching, while reducing the loop area that
can radiate EMI to the driver inputs and other
surrounding circuitry.
Many high-speed power circuits can be susceptible
to noise injected from their own output or other
external sources, possibly causing output re-
triggering. These effects can be especially obvious
if the circuit is tested in breadboard or non-optimal
circuit layouts with long input, enable, or output
leads. For best results, make connections to all pins
as short and direct as possible.
The turn-on and turn-off current paths should be
minimized as discussed in the following sections.
Figure 39 shows the pulsed gate-drive current path
Figure 38.
MillerDrive? Output Architecture
when the gate driver is supplying gate charge to turn the
MOSFET on. The current is supplied from the local
V DD Bypass Capacitor Guidelines
To enable this IC to turn a power device on quickly, a
local, high-frequency, bypass capacitor C BYP with low
ESR and ESL should be connected between the VDD
and GND pins with minimal trace length. This capacitor
bypass capacitor, C BYP , and flows through the driver to
the MOSFET gate and to ground. To reach the high
peak currents possible, the resistance and inductance in
the path should be minimized. The localized C BYP acts to
contain the high peak-current pulses within this driver-
MOSFET circuit, preventing them from disturbing the
sensitive analog circuitry in the PWM controller.
is in addition to bulk electrolytic capacitance of 10μF to
47μF often found on driver and controller bias circuits.
A typical criterion for choosing the value of C BYP is to
keep the ripple voltage on the V DD supply ≤ 5%. Often
this is achieved with a value ≥ 20 times the equivalent
load capacitance C EQV , defined here as Q gate /V DD .
Ceramic capacitors of 0.1μF to 1μF or larger are
common choices, as are dielectrics, such as X5R and
X7R, which have good temperature characteristics and
high pulse current capability.
PWM
C BYP
V DD
FAN3111
V DS
If circuit noise affects normal operation, the value of
C BYP may be increased to 50-100 times the C EQV or C BYP
may be split into two capacitors. One should be a larger
value, based on equivalent load capacitance, and the
other a smaller value, such as 1-10nF, mounted closest
to the VDD and GND pins to carry the higher-frequency
components of the current pulses.
Figure 39. Current Path for MOSFET Turn-On
Figure 40 shows the current path when the gate driver
turns the MOSFET off. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn-off times, the resistance and
inductance in this path should be minimized.
Layout and Connection Guidelines
V DD
V DS
The FAN3111 incorporates fast reacting input circuits,
short propagation delays, and output stages capable of
delivering current peaks over 1A to facilitate voltage
transition times from under 10ns to over 100ns. The
following layout and connection guidelines are strongly
recommended:
? Keep high-current output and power ground paths
separate from logic input signals and signal ground
C BYP
PWM
FAN3111
paths. This is especially critical when dealing with
TTL-level logic thresholds.
Figure 40.
Current Path for MOSFET Turn-Off
? 2008 Fairchild Semiconductor Corporation
FAN3111 ? Rev. 1.0.3
13
www.fairchildsemi.com
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